Semiconductor chips (dices, integrated circuits) are the most important building hardware in modern information society. Circuitry functional blocks of different functions are integrated into a chip, and different circuitry functional blocks have different requirements of supply voltage(s); therefore, different power domains are arranged inside the chip for providing different supply voltages. For example, input/output circuits of a chip for exchanging data and signals with external via input/output (I/O) pads need higher supply voltage of, e.g., 3.3 Volts; on the other hand, core circuit of a chip, such as logic operation circuitry, operates in lower supply voltage of, e.g., 1.8 Volts. Power required for chip operation is drained from external via power pads of a chip, and different supply voltages are transmitted to circuitry functional blocks of different power domains by various power rails inside the chip.
As semiconductor manufacture process evolves toward advanced process of deep sub-micron, advanced devices (e.g., transistors) of smaller area, lower power consumption and higher speed are utilized to construct circuitry functional blocks inside a chip. However, due to low voltage tolerance of advanced devices, advanced devices are suitable for circuitry functional blocks of low supply voltage rather than circuitry functional blocks of high supply voltage.
To prevent chip damage caused by electro-static discharge (ESD) during transportation, processing, assembly and testing, ESD protection mechanism is arranged in a chip, and the externally exposed power pads and I/O pads of a chip are key spots for implementation of the ESD protection mechanism. For example, an ESD protection circuit can be arranged between a first power rail and a second power rail, in cooperation with a conductive discharge path arranged between an I/O pad and the first power rail. With such arrangement, when an ESD event occurs between the I/O pad and a power pad of the second power rail, current of ESD can be conducted from the I/O pad to the first power rail by the discharge path, and then be conducted to the second power rail by the ESD protection circuit, so the current of ESD flows out of the chip via the power pad of the second power rail with other circuitry functional blocks bypassed, thus ESD protection is achieved.
In an ESD protection circuit of a prior art, two staked transistors are included; source-drain channels of the two transistors are serially connected between power rails of 3.3 Volts and 0 Volts (ground), and a gate is coupled to a power rail of 1.8 Volts. To work with such ESD protection circuit, an I/O circuit needs two p-channel metal-oxide-semiconductor (MOS) transistors stacked between the 3.3 Volts power rail and an I/O pad, and another two n-channel MOS transistors stacked between the I/O pad and the 0 Volts power rail. These two pairs of stacked transistors are not only used to drive signal output, but also used to conduct the I/O pad to the 3.3 Volts power rail or the 0 Volts power rail during ESD events.
A shortcoming of the prior art is that the ESD protection demands larger layout area to implement the two pairs of stacked MOS transistors, and therefore degrades chip integrity and enlarges total area of chip.
In an ESD protection circuit of another prior art, serial resistor-capacitor is arranged between the 3.3 Volts power rail and the 0 Volts power rail to detect whether ESD event occurs, a voltage at a node between the resistor and the capacitor is inverted by an inverter to control conduction of a clamp transistor. The inverter operates between the 3.3 Volts power rail and the 0 Volts power rail; a drain and a source of the clamp transistor are also coupled between the 3.3 Volts power rail and the 0 Volts power rail, and a gate is controlled by the inverter.
From the aforementioned description, it is recognized that these ESD protection circuits of prior arts need to operate under high supply voltage of 3.3 Volts, and are difficult to be implemented by advanced devices.